1. Field of the Invention
The present invention relates to a simulation model of a Bias Temperature (BT) instability of a field-effect transistor and a modeling method thereof. Furthermore, the present invention relates to a simulation device that uses the simulation model, and a semiconductor integrated circuit device designed through applying a simulation program that uses the simulation model.
2. Description of the Related Art
A reliability simulation in a design of a semiconductor integrated circuit is important as the means by which the semiconductor integrated circuit confirms, for example, the guarantee of proper operation for ten years (guarantee that the function can be maintained for ten years). As the factor of the time dependent instability that should be considered for a reliability assurance of a transistor, a BT instability, a hot-carrier deterioration, and a Time Dependent Dielectric Breakdown (TDDB) or the like are quoted. The BT indicates an applied bias and an operating temperature when the characteristic is deteriorated according to the applied bias condition and the temperature condition of a semiconductor device (chip).
In order to achieve a transistor that has a high electric current ability under lower power, it is important to achieve a thin film of a gate oxide film provided between the gate and silicon substrates of the transistor. In the improvement of the reliability of the semiconductor integrated circuit and the transistor, measures against rising of the threshold voltage and the decrease in the electric current ability that is generated due to the BT instability will be much more importance in the future. It is considered that the BT instability occurs as a result that the interface state and the fixed charge are generated since the Si to H (silicon-hydrogen) bond at interface between gate oxide film and silicon substrate of the transistor may break and the hydrogen atom penetrates into oxide film. However, everything of the physical phenomenon has not been clarified.
In a MOS transistor in the semiconductor integrated circuit, Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) are generated depending on the bias condition. Both of these instabilities degenerate the electrical characteristics of the transistor with time.
One of the models of the BT instability of a conventional transistor is set on the assumption that the surface potential distribution of the substrate under the gate becomes constant along a channel. This can be referred to in a non-patent document 1 (Vijay Reddy, et al., “Impact of Negative Bias Temperature Instability on Digital Circuit Reliability”, Texas Instruments). For example, in an inverter circuit, the NBTI is examined under each bias condition of “gate terminal is −2.8V” and “drain terminal, source terminal, and substrate terminal are 0V” in a PMOS transistor group that configures the relevant inverter circuit. And then, the discussion in a circuit scale (circuit where at least one of the NMOS transistors and the PMOS transistors exist respectively) is performed by being applied the examination result of the PMOS transistor group to the aforementioned inverter circuit.
Moreover, other one of the models of the BT instability of the transistor is set on the assumption that the variation of the electrical characteristic of the transistor due to the BT instability is occurred because of a time dependent change in the electric charge near the interface between the substrate surface and the gate oxide film. Further, this model is set so that the concentration change of the electric charge on the substrate surface influences the threshold voltage directly. This can be referred to in a non-patent document 2 (M. A. Alam, “A Critical Examination of the Mechanics of Dynamic NBTI for PMOS FETs”, Agere Systems).
The model of the BT instability of a conventional transistor described above is set in consideration of only the condition that the BT instability becomes largest (worst condition) based on assumption that the substrate surface potential (electrical potential) under the gate of the transistor is constant in the entire area on the substrate surface under the gate. More specifically, in the case of the modeling of the NBTI of the PMOS transistor, the model is created through giving the gate terminal a negative electrical potential, and setting up the drain terminal, the source terminal and the substrate terminal as 0V together, and then the simulation model is set by fixing the gate terminal to 0V and giving a positive same electrical potential to the drain terminal, the source terminal and the substrate terminal. In the model setting, it is assumed that it becomes a condition in which the BT instability occurs most easily in the entire area of the oxide film under the gate when the above-mentioned electrode bias of the terminal is given.
However, in an actual transistor operation on the semiconductor integrated circuit, for example, in the transistor in the circuit that performs analog operation, it is not likely that the drain terminal, the source terminal and the substrate terminal always operate at same electrical potential like the transistor in the inverter circuit. Furthermore, when the electrode bias of the drain terminal, the source terminal and the substrate terminal are mutually different, the potential of the substrate surface under the gate does not actually become constant in the entire area on the substrate surface under the gate. Therefore, when the bias potential of the drain terminal, the source terminal and the substrate terminal is treated as the same electrical potential, it becomes impossible to estimate the amount of the transistor of the electrical characteristic deterioration with high accuracy. The reason is explained below.
For example, in designing an operable semiconductor integrated circuit even after ten years, there is a case that the circuit operating after ten years is simulated by applying the shift of the threshold voltage and the decrease in the electric current ability estimated by the terminal bias, at which a BT instability becomes the worst case, to the semiconductor integrated circuit. In this case, it becomes a circuit operating simulation result that reflects a variation quantity that is bigger than the one where an actual semiconductor integrated circuit varies for ten years (Excess deterioration determination). And then, there is an advantage that an operable semiconductor integrated circuit after ten years will be actually fabricated if the semiconductor integrated circuit is designed based on the simulation result of such an excess deterioration determination. However, there is a problem that it becomes an excessive quality design that the semiconductor integrated circuit that has an excessive design allowance that exceeded the design allowance of the circuit necessary for operating after ten years aiming, for example, an operable semiconductor integrated circuit after 50 years is fabricated. Moreover, there is a problem that it causes the area growing more than the necessity.